Serial Array Time Slot Interchangers and Optical Implementations

We consider time slot interchangers (TSIs) which are built from 2×2 exchange switches and delays and which are useful for time division multiplexed (TDM) systems in telecommunications and pipelined systems such as time multiplexed optical multiprocessors. We formulate a general method for constructing TSIs based on multistage interconnection networks in the space domain via space-to-time mapping. Two types of TSIs, time slot permuters and time slot sorters, are considered. We review the time slot permuter based on the Benes v network, and obtain the Λ̃ time slot permuter based on the bit-controlled, self-routing Λ permutation network. The time slot sorter, SN , is obtained from the Batcher spatial sorting network. The generalized Lambda time slot permuter ΛN is obtained, in an algorithmic approach, by combining the idea of the Λ̃ time slot permuter and Q -way bitonic decomposition (Q =2q ). The numbers of switches, control complexities, and frame delays of these architectures are compared, and the problem of crosstalk in optical implementation is discussed. It will be shown that control complexity can be traded against the number of switches. Index terms — Time slot interchange, permutation networks, Batcher sorting networks, time multiplexing, bitonic sorters, optical switching, permutation control. hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh H.F. Jordan and S.V. Ramanan are with the Optoelectronic Computing Systems Center at the University of Colorado, Boulder, CO 80309-0525. D. Lee and K.Y. Lee are with the University of Denver, Denver, CO 80208. H.F. Jordan and S.V. Ramanan were supported in part by the National Science Foundation Engineering Research Center Grant No. ECD 9015128 and by the Colorado Advanced Technology Institute (CATI). K.Y. Lee was supported in part by National Science Foundation Grant No. MIP-9210605.